Configurable register circuitry for error detection and recovery

ABSTRACT

Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.

This application is a continuation-in-part of application Ser. No.14/164,047, filed Jan. 24, 2014, which is hereby incorporated byreference herein in its entirety.

BACKGROUND

This invention relates to integrated circuits and, more particularly, toconfigurable register circuitry with error detection and error recoverycapabilities in integrated circuits.

Every transition from one technology node to the next technology nodehas resulted in smaller transistor geometries and thus potentially morefunctionality implemented per unit of integrated circuit area.Synchronous integrated circuits have further benefited from thisdevelopment as evidenced by reduced interconnect and cell delays, whichhas led to performance increases. However, more recent technology nodeshave seen a significant slow-down in the reduction of delays and thus toa slow-down in the performance increase.

Timing analysis is usually performed to determine the delay of pathsbetween synchronous elements. The delay of the longest-delay path, whichis sometimes also referred to as the critical path delay, determines theclock rate at which the synchronous elements in the integrated circuitsare triggered. Timing analysis is required to account for the worst casescenarios and needs to take variability in combinational logic delayscaused by manufacturing or environmental variations into account. Inmany cases, additional timing guard bands are required to ensure properoperation across manufacturing and environmental variations leading tooverly pessimistic timing requirements and thus to slow clock rates.

Furthermore, some synchronous designs implemented in integrated circuitssuch as data paths in packet processing applications are tolerant ofoccasional timing faults caused by timing variability. Such timingvariability tolerant designs are often able to handle the occasionaltiming fault, especially when the timing fault can be detected.

SUMMARY

In accordance with certain aspects of the invention, an integratedcircuit such as a programmable logic integrated circuit may have firstand second inputs and include a multiplexer, first and second registers,and a comparator.

The multiplexer may receive a predetermined configuration bit from amemory element and first and second signals from the first and secondinputs. The multiplexer may further select between the first and secondsignals based on the predetermined configuration bit.

The first and second registers may be triggered based on a first andsecond clock signal, respectively. The first and second registers mayfurther receive and store the first and second signals from the firstand second input ports, respectively.

The comparator may receive the stored first and second signals from thefirst and second registers and generate a status signal based on acomparison of the stored first and second signals. For example, thecomparator may generate the status signal as a result of a logicexclusive OR function of the stored first and second signals.

It is appreciated that the present invention can be implemented innumerous ways, such as a process, an apparatus, a system, a device, orinstructions executed on a programmable processor. Several inventiveembodiments are described below.

In certain embodiments, the above-mentioned integrated circuit mayfurther include an additional multiplexer. The additional multiplexermay receive an additional predetermined configuration bit from anadditional memory element, the status signal from the comparator and thestored selected signal from the second register. The additionalmultiplexer may select between the status signal and the stored selectedsignal based on the additional predetermined configuration bit.

If desired, the above-mentioned integrated circuit may further include alogic exclusive OR gate that receives the first clock signal and asecond additional predetermined configuration bit from a secondadditional memory element. The logic exclusive OR gate may invert thefirst clock signal to generated the second clock signal based on thesecond additional predetermined configuration bit.

Further features of the invention, its nature and various advantages,will be more apparent from the accompanying drawings and the followingdetailed description of the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram of an illustrative programmable integrated circuitwith programmable logic regions in accordance with an embodiment.

FIG. 1B is a diagram of an illustrative logic region in accordance withan embodiment.

FIG. 2 is a diagram of an illustrative synchronous circuit in accordancewith an embodiment.

FIG. 3A is a diagram of illustrative register circuitry that isconfigurable as two independent registers or as one register with errordetection and error recovery circuitry in accordance with an embodiment.

FIG. 3B is a diagram of an illustrative waveform showing the operationof the register circuitry of FIG. 3A in error detection and errorrecovery mode in accordance with an embodiment.

FIG. 4A is a diagram of illustrative register circuitry that isconfigurable as two independent registers or as one register with errordetection and error recovery circuitry in the next clock cycle inaccordance with an embodiment.

FIG. 4B is a diagram of an illustrative waveform showing the operationof the register circuitry of FIG. 4A in error detection and errorrecovery mode in accordance with an embodiment.

FIG. 5 is a diagram of illustrative register circuitry that isconfigurable as two independent registers or as one register with errordetection and error recovery circuitry in either the current or the nextclock cycle in accordance with an embodiment.

FIG. 6 is a diagram of illustrative register circuitry that isconfigurable as two independent registers or as one register with errordetection circuitry in case of single event upsets in accordance with anembodiment.

FIG. 7A is a diagram of illustrative clock selection circuitry inaccordance with an embodiment.

FIG. 7B is a diagram of illustrative clock selection circuitry withconfigurable clock signal inversion circuitry in accordance with anembodiment.

FIG. 7C is a diagram of illustrative clock selection circuitry withconfigurable clock signal delay circuitry in accordance with anembodiment.

FIG. 8 is a flow chart showing illustrative steps for operatingconfigurable register circuitry in error detection and recovery mode inaccordance with an embodiment.

DETAILED DESCRIPTION

The present invention relates to integrated circuits such asprogrammable integrated circuits and more particularly to integratedcircuits with configurable register circuitry.

As previously described, some synchronous designs implemented inintegrated circuits such as data paths in packet processing applicationsare tolerant of occasional timing faults caused by timing variability.For example, a data packet dropped during the streaming of a video orduring a phone conversation using a voice over internet protocol (VoIP)methodology may not be noticeable and thus may be acceptable. Suchtiming variability tolerant designs are often able to handle theoccasional timing fault, especially when the timing fault can bedetected.

It may therefore be desirable to provide register circuitry that may beconfigured to operate as conventional registers when the integratedcircuit implements a timing variability intolerant design and asregisters with error detection and error correction capabilities whenthe integrated circuit implements a timing variability tolerant design.Thus, a timing variability tolerant design may operate at a higher clockrate in an integrated circuit when the register circuitry is configuredto operate as registers with error detection and error correctioncapabilities than when the register circuitry is configured to operateas conventional registers.

It will be recognized by one skilled in the art, that the presentexemplary embodiments may be practiced without some or all of thesespecific details. In other instances, well-known operations have notbeen described in detail in order not to unnecessarily obscure thepresent embodiments.

An illustrative embodiment of an integrated circuit such as aprogrammable logic device 100 in accordance with the present inventionis shown in FIG. 1.

Programmable logic device 100 has input/output circuitry 110 for drivingsignals off of device 100 and for receiving signals from other devicesvia input/output pins 120. Interconnection resources 115 such as globaland local vertical and horizontal conductive lines and buses may be usedto route signals on device 100.

Input/output circuitry 110 include conventional input/output circuitry,serial data transceiver circuitry, differential receiver and transmittercircuitry, or other circuitry used to connect one integrated circuit toanother integrated circuit.

Interconnection resources 115 include conductive lines and programmableconnections between respective conductive lines and are thereforesometimes referred to as programmable interconnects 115.

Programmable logic region 140 may include programmable components suchas digital signal processing circuitry, storage circuitry, arithmeticcircuitry, or other combinational and sequential logic circuitry such asconfigurable register circuitry. As an example, the configurableregister circuitry may operate as a conventional register.Alternatively, the configurable register circuitry may operate as aregister with error detection and error correction capabilities.

The programmable logic region 140 may be configured to perform a customlogic function. The programmable logic region 140 may also includespecialized blocks that perform a given application and have limitedconfigurability. For example, the programmable logic region 140 mayinclude specialized blocks such as configurable storage blocks,configurable processing blocks, programmable phase-locked loopcircuitry, programmable delay-locked loop circuitry, or otherspecialized blocks with limited configurability. The programmableinterconnects 115 may also be considered to be a type of programmablelogic region 140.

Programmable logic device 100 contains programmable memory elements 130.Memory elements 130 can be loaded with configuration data (also calledprogramming data) using pins 120 and input/output circuitry 110. Onceloaded, the memory elements each provide a corresponding static controlsignal that controls the operation of an associated logic component inprogrammable logic region 140. In a typical scenario, the outputs of theloaded memory elements 130 are applied to the gates ofmetal-oxide-semiconductor transistors in programmable logic region 140to turn certain transistors on or off and thereby configure the logic inprogrammable logic region 140 and routing paths. Programmable logiccircuit elements that may be controlled in this way include parts ofmultiplexers (e.g., multiplexers used for forming routing paths inprogrammable interconnects 115), look-up tables, logic arrays, AND, OR,NAND, and NOR logic gates, pass gates, etc.

Memory elements 130 may use any suitable volatile and/or non-volatilememory structures such as random-access-memory (RAM) cells, fuses,antifuses, programmable read-only-memory memory cells, mask-programmedand laser-programmed structures, combinations of these structures, etc.Because memory elements 130 are loaded with configuration data duringprogramming, memory elements 130 are sometimes referred to asconfiguration memory, configuration RAM, or programmable memoryelements.

The circuitry of device 100 may be organized using any suitablearchitecture. As an example, the logic of programmable logic device 100may be organized in a series of rows and columns of larger programmablelogic regions each of which contains multiple smaller logic regions. Thesmaller regions may be, for example, regions of logic that are sometimesreferred to as logic elements (LEs), each containing a look-up table,one or more registers, and programmable multiplexer circuitry. Thesmaller regions may also be, for example, regions of logic that aresometimes referred to as adaptive logic modules (ALMs), configurablelogic blocks (CLBs), slice, half-slice, etc. Each adaptive logic modulemay include a pair of adders, a pair of associated registers and alook-up table or other block of shared combinational logic (i.e.,resources from a pair of LEs—sometimes referred to as adaptive logicelements or ALEs in this context). The larger regions may be, forexample, logic array blocks (LABs) or logic clusters of regions of logiccontaining for example multiple logic elements or multiple ALMs.

During device programming, configuration data is loaded into device 100that configures the programmable logic regions 140 so that their logicresources perform desired logic functions. For example, theconfiguration data may configure a portion of the configurable registercircuitry to operate as a conventional register. If desired, theconfiguration data may configure some of the configurable registercircuitry to operate as a register with error detection and errorcorrection capabilities.

FIG. 1B shows an illustrative diagram of a logic region 150. As shown inFIG. 1b , logic region 150 may include look-up table circuitry 160,adder circuitry 165, register circuitry 170, and configurableinterconnect circuitry 175. Look-up table circuitry 160 may include oneor more configurable look-up tables. For example, look-up tablecircuitry may include four three-input look-up tables which may beconfigured to implement two independent four-input look-up tables, onefive-input look-up table, or two five-input look-up tables which shareat least two inputs, etc.

Adder circuitry 165 may include one or more adders. Each of these addersmay implement a half-adder, a full-adder, a carry-save adder, aripple-carry adder, a carry-look ahead adder, or any other suitableadder circuitry.

Register circuitry 170 may include registers, latches, time-borrowingflip-flops (TBFF) or any other synchronous circuitry that is controlledby a clock signal. If desired, register circuitry 170 may containseveral different synchronous elements such as registers and latches, orregisters and time-borrowing flip-flops, just to name a fewcombinations.

Internal interconnection resources 180 such as conductive lines andbusses may be used to send data from one component to another componentor to broadcast data from one component to one or more other components.External interconnection resources 190 such as conductive lines andbusses may be used to communicate with external components. Externalinterconnection resources 190 may convey data signals between logicregion 150 and external components. If desired, external interconnectionresources may also convey control signals such as clock signals,asynchronous reset signals, etc.

Configurable interconnect circuitry 175 couples look-up table circuitry160, adder circuitry 165, and register circuitry 170 with each otherthrough internal interconnection resources 180 and to externalcomponents through external interconnection resources 190. Configurableinterconnect circuitry 175 may include memory elements (e.g., memoryelements 130 of FIG. 1A) which may be loaded with configuration dataduring device programming.

FIG. 2 shows an illustrative diagram of a synchronous circuit. Asynchronous circuit is characterized by one or more clock signals suchas clock signal 250, synchronous storage elements such as registers 210and 220 that are controlled by the clock signal, interconnects coupledbetween the synchronous elements (e.g., interconnect 230) to conveysignals between synchronous elements, and combinational logic such ascombinational logic 240 that may implement any desired logic function orcombinations of logic functions.

As an example, register circuitry 170 of a first logic region 150 (seeFIG. 1B) may include register 210 which may send a signal usinginterconnection resources 180, configurable interconnect circuitry 175,and external interconnection resources 190 to a second logic region 150.The second logic region may receive the signal and route the signalusing configurable interconnect circuitry 175 and internalinterconnection resources 180 to look-up table circuitry 160, which mayimplement the combinational logic 240. Logic region 150 may route theoutput of the combinational logic 240 using configurable interconnectcircuitry 175 and internal interconnect resources 180 from the look-uptable circuitry 160 to register circuitry 170 which may implementregister 220.

Dedicated clock lines, sometimes also referred to as a clock tree, maydistribute clock signals to all regions of an integrated circuit. Aclock tree may have dedicated connections that reduce the skew betweendifferent branches of the tree in an attempt to achieve simultaneousarrival of a clock signal at all the different sequential elements thatare controlled by that clock signal. The clock signal may trigger thesequential elements to store data signals available at their inputs. Forexample, a register may store a new data signal in response to receivinga rising edge of the clock signal at the register's clock input.Alternatively, a register may store a new data signal whenever a fallingclock edge of the clock signal arrives at the register's clock input.

Consider the scenario where registers 210 and 220 are both rising clockedge triggered registers controlled by the same clock signal 250. Inthis scenario, a signal that is stored in register 210 at a rising clockedge and conveyed over interconnection 230 and through combinationallogic 240 to register 220 is required to arrive at the data input ofregister 220 a given amount of time before the next rising edge of theclock signal reaches register 220. This given amount of time issometimes also referred to as setup time (Tsu). The data signal at thedata input 220 also needs to be stable for an additional amount of timeafter the rising edge of the clock signal has reached register 220. Thisadditional amount of time is sometimes also referred to as hold time(Th). Setup time (Tsu) and hold time (Th) of a register may be definedfor example in a data sheet or a library file. Setup time and hold timemay constrain the clock rate of the clock signal.

Setup time and hold time may vary significantly depending on ambienttemperature, supply voltage, and process technology, and these timingvariations need to be taken into account on various different levels.For example, the combinational logic between registers may be optimized,register pipelining may reduce the delay between any two registers, orthe clock rate may be adjusted. Any of these measures may be appliedalone or in combination to guard band against timing variability, whichmay otherwise produce timing faults.

Some synchronous designs may be able to tolerate occasional timingfaults caused by timing variability. FIG. 3A shows an embodiment ofconfigurable register circuitry 300 that may operate as conventionalregisters for a timing variability intolerant design and as registerswith error detection and error correction capabilities for a timingvariability tolerant design. Thus, a timing variability tolerant designmay operate at a higher clock rate when the register circuitry isconfigured to operate as registers with error detection and errorcorrection capabilities than when the register circuitry is configuredto operate as conventional registers.

As shown in FIG. 3A, configurable register circuitry 300 may includeregisters 360 and 370, multiplexer 390, logic exclusive OR gate 380, andconfiguration memory 332, 342, 352, and 397 that configure multiplexers330, 340, 350, and 395 respectively. For example, the configurableregister circuitry may be configured to operate as two independentregisters. In this configuration, which is sometimes also referred to as“normal configuration”, configuration memory 352 may configuremultiplexer 350 to select the signal from wire 320. Thus, register 360may store the signal conveyed by wire 320, while register 370 may storethe signal conveyed by wire 310. Configurable memory element 397 mayconfigure multiplexer 395 to select the signal arriving directly fromregister 370, and the output produced by logic exclusive OR gate 380 maybe discarded in this configuration. Configuration memory 332 and 342 mayconfigure multiplexers 330 and 340 to select any of the clock signals tocontrol registers 370 and 360, respectively.

As another example, configurable register circuitry 300 may beconfigured to operate as one register with error detection and errorcorrection capabilities. In this configuration, which is sometimes alsoreferred to as “error-detecting configuration”, configuration memory 352may configure multiplexer 350 to select the signal conveyed by wire 310.Thus, both registers (i.e., registers 360 and 370) may store the samesignal. Configuration memory 332 may configure multiplexer 330 to selecta predetermined clock signal, and configuration memory 342 may configuremultiplexer 340 to select the same predetermined clock signal delayed bya given duration.

Configuration memory 397 may configure multiplexer 395 to select thesignal arriving from multiplexer 390, and multiplexer 390 may propagatethe signal from register 370 for as long as registers 370 and 360 havethe same value. In the event that registers 360 and 370 store differentvalues, logic exclusive OR gate 380 may switch polarity and directmultiplexer 390 to select the signal from register 360.

FIG. 3B is a diagram of an illustrative waveform showing the operationof the configurable register circuitry 300 of FIG. 3A in error detectionand error recovery mode with CLK0 and CLK1 representing the clocksignals selected by multiplexers 330 and 340, respectively. The signalINPUT may represent the signal conveyed over wire 310, REG0 and REG1 thesignals at the outputs of registers 370 and 360, XOR_OUT the signal atthe output of logic exclusive OR gate 380, and MUX_OUT the signal at theoutput of multiplexer 395.

As an example, consider the scenario in which timing variability causesthe signal conveyed over wire 310 to arrive at time 305, while the clocksignal CLK0 has a rising clock edge at time 303 which is before thetransition of signal INPUT and the clock signal CLK1 has a rising clockedge at time 307 which is after the transition of signal INPUT. Thisimplies that the signal conveyed over wire 310 arrives at register 370later than the clock signal selected by multiplexer 330 and at register360 before the clock signal selected by multiplexer 340.

In this scenario, register 360 may store a different signal thanregister 370 as illustrated by signals REG0 and REG1 in FIG. 3B. Inother words, register 370 may store a faulty signal (i.e., an erroroccurred) while register 360 stores the correct signal. Logic exclusiveOR gate 380 may detect the error and produce a corresponding errordetection signal as illustrated by signal XOR_OUT at time 307. Logicexclusive OR gate 380 may also direct multiplexer 390 to select thesignal from register 360 (i.e., the correct signal) for propagation tomultiplexer 395 instead of selecting the signal from register 370 (i.e.,the faulty signal) for propagation to multiplexer 395, therebyperforming error correction as illustrated by signal MUX_OUT at time307.

Configurable register circuitry 300 of FIG. 3A may store a faulty signalin register 370 and perform error correction at the output usingmultiplexer 390. If desired, the error correction may be performed suchthat the register stores the corrected signal at the next rising clockedge. FIG. 4A shows an embodiment of such configurable registercircuitry 400 that, similar to configurable register circuitry 300 inFIG. 3A, may operate as conventional registers for a timing variabilityintolerant design and as registers with error detection and errorcorrection capabilities for a timing variability tolerant design.

As shown in FIG. 4A, configurable register circuitry 400 may includeregisters 460 and 470, multiplexer 484, logic exclusive OR gate 480, andconfiguration memory 486, 432, 442, and 452 that configure logic ANDgate 482 and multiplexers 430, 440, and 450 respectively.

As an example, configurable register circuitry 400 may be configured tooperate as two independent registers. In this configuration,configuration memory 452 may configure multiplexer 450 to select thesignal from wire 420. Thus, register 460 may store the signal conveyedby wire 420. Configurable memory element 486 may configure logic ANDgate 482 to disable access to multiplexer 484. For example,configuration memory element 486 may store a logic “0” to disable accessto multiplexer 484 and logic “1” to enable access to multiplexer 484.Thus, when access to multiplexer 484 is disabled, multiplexer 484 mayselect the signal from wire 410. The output produced by logic exclusiveOR gate 480 may be discarded in this configuration. Configuration memory432 and 442 may configure multiplexers 430 and 440 to select any of theclock signals 425 to control registers 470 and 460, respectively.

As another example, configurable register circuitry 400 may beconfigured to operate as one register with error detection and errorcorrection capabilities. In this configuration, configuration memory 452may configure multiplexer 450 to select the signal conveyed by wire 410,and multiplexer 484 may initially be configured to select the samesignal conveyed by wire 410. Thus, both registers (i.e., registers 460and 470) may store the same signal. Configuration memory 432 mayconfigure multiplexer 430 to select a predetermined clock signal, andconfiguration memory 442 may configure multiplexer 440 to select thesame predetermined clock signal delayed by a given duration.

Configuration memory 486 may configure logic AND gate 482 to enableaccess from logic exclusive OR gate 480 to multiplexer 484, andmultiplexer 484 may propagate the signal from wire 410 for as long asthe signals stored in registers 470 and 460 have the same value. In theevent that registers 460 and 470 store signals that have differentvalues, logic exclusive OR gate 480 may switch polarity, which may causethe output of logic AND gate 482 to switch polarity and thus directmultiplexer 484 to select the signal from register 460.

FIG. 4B is a diagram of an illustrative waveform showing the operationof the configurable register circuitry 400 of FIG. 4A in error detectionand error recovery mode with CLK0 and CLK1 representing the clocksignals selected by multiplexers 430 and 440, respectively. The signalINPUT may represent the signal conveyed over wire 410, REG0 and REG1 thesignals at the outputs of registers 470 and 460, AND_OUT the signal atthe output of logic AND gate 482, XOR_OUT the signal at the output oflogic exclusive OR gate 480, and MUX_OUT the signal at the output ofmultiplexer 484.

As an example, consider the scenario in which timing variability causesthe signal conveyed over wire 410 to arrive at time 405, while the clocksignal CLK0 has a rising clock edge at time 403 which is before thetransition of signal INPUT and the clock signal CLK1 has a rising clockedge at time 407 which is after the transition of signal INPUT. Thisimplies that the signal conveyed over wire 410 arrives at register 470later than the clock signal selected by multiplexer 430 and at register460 before the clock signal selected by multiplexer 440. In thisscenario, register 460 may store a different signal than register 470 asillustrated by signals REG1 and REG0, respectively. In other words,register 470 may store a faulty signal (i.e., an error occurred) whileregister 460 stores the correct signal. Logic exclusive OR gate 480 maydetect the error and produce a corresponding error detection signal asillustrated by signal XOR_OUT. Configuration memory 486 may configurelogic AND gate 482 to propagate the error detection signal from logicexclusive OR gate 480 to multiplexer 484 as illustrated by signalAND_OUT, which in response may select the signal from register 460(i.e., the correct signal) for propagation to register 470 asillustrated by signal MUX_OUT, where the faulty signal may be correctedone clock cycle later.

FIG. 5 shows another embodiment of configurable register circuitry 500that, similar to configurable register circuitry 300 in FIG. 3A andconfigurable register circuitry 400 in FIG. 4A, may operate as twoindependent conventional registers for a timing variability intolerantdesign and as a single registers with error detection and errorcorrection capabilities for a timing variability tolerant design.

As shown in FIG. 5, configurable register circuitry 500 may includeregisters 560 and 570, multiplexers 584 and 590, logic exclusive OR gate580, and configuration memory 583, 532, 542, 552, 587, and 589 thatconfigure logic AND gate 582 and multiplexers 530, 540, 550, 586, and588 respectively.

As an example, configurable register circuitry 500 may be configured tooperate as two independent registers. In this configuration,configuration memory 552 may configure multiplexer 550 to select thesignal from wire 520. Thus, register 560 may store the signal conveyedby wire 520. Configurable memory element 586 may configure logic ANDgate 582 to disable access to multiplexer 484. Thus, multiplexer 584 mayselect the signal from wire 510. Configurable memory element 589 mayconfigure multiplexer 588 to select the signal arriving from register570, and configurable memory element 587 may configure multiplexer 586to select the signal arriving from register 560. Configuration memory532 and 542 may configure multiplexers 530 and 540 to select any of theclock signals 525 to control registers 570 and 560, respectively.

As another example, configurable register circuitry 500 may beconfigured to operate as one register with error detection and errorcorrection capabilities. In this configuration, configuration memory 552may configure multiplexer 550 to select the signal conveyed by wire 510,and multiplexer 584 may initially be configured to select the samesignal conveyed by wire 510. Thus, both registers (i.e., registers 560and 570) may store the same signal.

Configuration memory 532 may configure multiplexer 530 to select apredetermined clock signal, and configuration memory 542 may configuremultiplexer 540 to select the same predetermined clock signal delayed bya given duration. Configurable register circuitry 500 may be configuredto provide error correction at the same clock cycle or at the next clockcycle. For example, configuration memory 589 may direct multiplexer 588to select the input connected to register 570, configuration memory 583may configure logic AND gate 582 to enable access from logic exclusiveOR gate 580 to multiplexer 584, and multiplexer 584 may propagate thesignal from wire 510 for as long as the signals stored in registers 570and 560 have the same value. In the event that registers 560 and 570store signals that have different values, logic exclusive OR gate 580may switch polarity, which may cause the output of logic AND gate 582 toswitch polarity and thus direct multiplexer 584 to select the signalfrom register 560, thereby performing error correction at the next clockcycle.

If desired, configuration memory 589 may direct multiplexer 588 toselect the input connected to multiplexer 590, configuration memory 583may configure logic AND gate 582 to disable access from logic exclusiveOR gate 580 to multiplexer 584, and thus multiplexer 584 may propagatethe signal from wire 510 to register 570. In the event that registers560 and 570 store signals that have different values, logic exclusive ORgate 580 may switch polarity, which may direct multiplexer 590 to selectthe signal from register 560, thereby performing error correction at thesame clock cycle.

As an example, consider the scenario in which timing variability causesthe signal conveyed over wire 510 to arrive at register 570 later thanthe clock signal selected by multiplexer 530 and at register 560 beforethe clock signal selected by multiplexer 540. In this scenario, register560 may store a different signal than register 570. In other words,register 570 may store a faulty signal (i.e., an error occurred) whileregister 560 stores the correct signal. Logic exclusive OR gate 580 maydetect the error and produce a corresponding error detection signal.Configuration memory 587 may direct multiplexer 586 to propagate theerror detection signal to downstream circuitry.

Configuration memory 583 may configure logic AND gate 582 to propagatethe error detection signal from logic exclusive OR gate 580 tomultiplexer 584, which in response may select the signal from register560 (i.e., the correct signal) for propagation to register 570, wherethe faulty signal may be corrected one clock cycle later.

If desired, configuration memory 589 may direct multiplexer 588 toselect the input connected to multiplexer 590, and multiplexer 590 mayselect the input connected to register 560 based on the error detectionsignal produced by logic exclusive OR gate 580, thereby correcting thefaulty signal in the same clock cycle.

Configurable register circuitry 300, 400, and 500 may be configured toprovide protection against single event upsets when operated in errordetection and error correction mode. In this configuration, registers360 and 370 in FIG. 3A are triggered by the same clock signal, registers460 and 470 in FIG. 4A are triggered by the same clock signal, andregisters 560 and 570 in FIG. 5 are triggered by the same clock signal.In other words, configuration memory 332 and 342 direct multiplexers 330and 340 to select the same clock signal, configuration memory 432 and442 direct multiplexers 430 and 440 to select the same clock signal, andconfiguration memory 532 and 542 direct multiplexers 530 and 540 toselect the same clock signal.

FIG. 6 shows an embodiment of configurable register circuitry 600 thatmay be configured to operate as two independent registers, as a singleregister with detection of single event upsets, or as a single registerwith detection of timing faults caused by timing variability.

As shown in FIG. 6, configurable register circuitry 600 may includeregisters 660 and 670, logic exclusive OR gate 680, and configurationmemory 632, 642, 652, and 687 that configure multiplexers 630, 640, 650,and 686 respectively. For example, the configurable register circuitrymay be configured to operate as two independent registers. In thisconfiguration, configuration memory 652 may configure multiplexer 650 toselect the signal from wire 620. Thus, register 660 may store the signalconveyed by wire 620, while register 670 may store the signal conveyedby wire 610. Configurable memory element 687 may configure multiplexer686 to select the signal arriving directly from register 660, andconfiguration memory 632 and 642 may configure multiplexers 630 and 640to select any of the clock signals 625 to control registers 670 and 660,respectively.

As another example, configurable register circuitry 600 may beconfigured to operate as one register with error detection capabilities.In this configuration, configuration memory 652 may configuremultiplexer 650 to select the signal conveyed by wire 610. Thus, bothregisters (i.e., registers 660 and 670) may store the same signal.

In the event that registers 660 and 670 store signals with differentvalues, logic exclusive OR gate 680 may indicate that an error hasoccurred. Configuration memory 687 may configure multiplexer 686 toselect the signal arriving from logic exclusive OR gate 680 and providethe selected signal as the error detection signal at an output ofconfigurable register circuitry 600.

When configurable register circuitry 600 is configured to detect errorscaused by timing variability, configuration memory 632 may configuremultiplexer 630 to select a predetermined clock signal, andconfiguration memory 642 may configure multiplexer 640 to select thesame predetermined clock signal delayed by a given duration.

As an example, consider the scenario in which timing variability causesthe signal conveyed over wire 610 to arrive at register 670 later thanthe clock signal selected by multiplexer 630 and at register 660 beforethe clock signal selected by multiplexer 640. In this scenario, register660 may store a different signal than register 670. In other words,register 670 may store a faulty signal (i.e., an error occurred) whileregister 660 stores the correct signal. Logic exclusive OR gate 680 maydetect the error and produce a corresponding error detection signal,which is propagated to downstream logic by multiplexer 686.

When configurable register circuitry 600 is configured to detect errorscaused by single-event upsets, configuration memory 632 may configuremultiplexer 630 to select a predetermined clock signal, andconfiguration memory 642 may configure multiplexer 640 to select thesame predetermined clock signal (i.e., both registers 660 and 670 storethe same signal based on the same clock signal).

As an example, consider the scenario in which an ion strike causes thesignal stored in register 670 to change polarity. In this scenario,register 660 may store a different signal than register 670. In otherwords, register 670 may store a faulty signal (i.e., an error occurred)while register 660 stores the correct signal. Logic exclusive OR gate680 may detect the error and produce a corresponding error detectionsignal, which is propagated to downstream logic by multiplexer 686.

For example, error handling circuitry may receive the error signal fromconfigurable register circuitry 600 and initiate error handling measuresaccording to a predefined protocol. As an example, consider theimplementation of a finite state machine (FSM), which uses configurableregister circuitry 600 for implementing state registers. If desired,error handling circuitry may receive error detection signals from theconfigurable register circuitry that implements the state registers. Theerror handling circuitry may perform a state transition of the finitestate machine from the faulty state to a safe state (e.g., the initialstate) whenever an error is detected.

The implementation of a circuit design in an integrated circuit such asprogrammable logic device 100 of FIG. 1 may include instantiations ofindividual registers, registers with error detection capabilities, andregisters with error detection and error correction capabilities. CADtools (e.g., logic synthesis, placement, and routing tools) may map thecircuit design onto the integrated circuit and select the appropriateconfigurable register circuitry and provide the correspondingconfiguration.

If desired, assignments may determine the configuration of a givenconfigurable register circuit when implementing a circuit design usingan integrated circuit (e.g., programmable logic device 100 of FIG. 1)with configurable register circuitry. For example, an assignment mayconfigure a configurable register circuit to operate as multipleindependent registers, as a single register with error detectioncapabilities, or a single register with error detection and errorcorrection capabilities.

Those assignments can be provided for individual configurable registercircuits, portions of the circuit design, or for the entire circuitdesign. For example, the assignments may be provided with the designspecification, the RTL description of the circuit design (e.g., as apragma or as an assertion), in an assignment file, or through user input(e.g., using a design and assignment entry tools), to name a few.

In certain embodiments, a given configurable register circuit may havemore than one assignment, which may be in conflict with each other e.g.,an assignment received with the design specification for a givenconfigurable register circuit may conflict with the assignment receivedwith the RTL description of the circuit design and with anotherassignment received with the assignment file. In this scenario, apredetermined priority of assignments, which may be defined explicitlyor resolved implicitly by CAD tools that implement the circuit design onthe integrated circuit, may determine which of the conflictingassignments is selected.

For example, the assignment from the user or an assignment file mayoverride the assignments received from other sources, and an assignmentreceived with the RTL description may override an assignment receivedwith the design specification.

The assignments may target the entire circuit design or portions of thecircuit design. For example, some assignments may be defined globallyand thus be applicable to the entire circuit design. Other assignmentsmay be assigned locally and thus be applicable only to the correspondingportions of the circuit design. Consider the scenario in which thecircuit design is organized hierarchically. In this scenario, everyhierarchical instance may include different assignments. In other words,multiple different assignments may target the same portion of thecircuit design, and priorities may be defined explicitly or resolvedimplicitly by CAD tools.

For example, an assignment defined at a higher level of the circuitdesign hierarchy may override an assignment at a lower level.Alternatively, an assignment defined at a lower level of the circuitdesign hierarchy may override an assignment at a higher level, orindividual levels of the circuit design hierarchy may be given priorityover other levels of circuit design hierarchy.

Assignments included in design specification or RTL description may beconveyed to CAD tools in the form of variables, parameters, compilerdirectives, macros, pragmas, or assertions, just to name a few. CADtools may use an assignment file, which may include a portion or all ofthe assignments. Such an assignment file may be included with designspecification or RTL description. In some scenarios, a portion or all ofthe assignments may be embedded in the circuit design. Alternatively,the assignments may have been defined using design and assignment entrytools.

As previously described, configuring configurable register circuitry tooperate as a single register with detection of timing faults caused bytiming variability requires the selection of a predetermined clocksignal for a first register and the selection of the same predeterminedclock signal delayed by given duration for a second register.

FIG. 7A shows an embodiment of a clock selection circuit which may beconfigured to select one of the clock signals 730 (e.g., clock signals325, 425, 525, or 625 of FIGS. 3 to 6, respectively) to control register710 (e.g., registers 360, 460, 560, or 660 of FIGS. 3 to 6,respectively). As shown, configuration memory 721 may choose one of theclock signals 730 at the inputs of multiplexer 720 for propagation toregister 710.

Another embodiment of a clock selection circuit is shown in FIG. 7B. Asshown, configuration memory 723 may direct multiplexer 722 to select oneof the clock signals 732. Logic exclusive OR gate 742 may eitherpropagate or invert the selected clock signal based on configurationmemory 752, thereby controlling register 712 with the selected clocksignal or the selected clock signal delayed by half a clock cycle.

Another embodiment of a clock selection circuit is shown in FIG. 7C. Asshown, configuration memory 725 may direct multiplexer 724 to select oneof the clock signals 734. The selected clock signal may be delayed by agiven duration by delay element 744, and configuration memory 764 maydirect multiplexer 754 to select between the selected clock signal frommultiplexer 724 and the delayed clock signal from delay element 744 tocontrol register 714.

The clock selection circuits shown in FIGS. 7A, 7B, and 7C are merelyillustrative and are not intended to limit the scope of the invention.If desired, the clock selection circuit may include multiple delayelements with different delays from which a multiplexer may select.Delay circuits may be arranged in series or in parallel, delay circuitsmay be combined with logic exclusive OR gates, etc.

FIG. 8 is a flow chart showing illustrative steps for operatingconfigurable register circuitry such as configurable register circuitry500 of FIG. 5 in error detection and recovery mode in accordance with anembodiment. During step 810, the configurable register circuitry mayreceive first and second signals at first and second inputs such assignals conveyed over wires 510 and 520, respectively. The configurableregister circuitry may select between the signals to produce a selectedsignal based on a predetermined configuration. For example,configuration memory 552 may direct multiplexer 550 to select the signalreceived on wire 510.

During step 820, a first register (e.g., register 570 of FIG. 5) inconfigurable register circuitry may store the first signal based on afirst clock signal, and a second register (e.g., register 560 of FIG. 5)in configurable register circuitry may store the selected signal basedon a second clock signal. For example, the second clock signal may bethe first clock signal delayed by a predetermined duration.

During step 830, a comparator (e.g., logic exclusive OR gate 580 of FIG.5) in configurable register circuitry may compare the stored firstsignal and the stored selected signal to detect whether the stored firstsignal is different than the stored selected signal. A difference in thetwo signals may indicate the detection of an error.

In response to detecting that the stored first signal and the storedselected signal have different values, the configurable registercircuitry may route the stored selected signal to an output during step845, thereby providing an error corrected signal at the output. Forexample, configuration memory 589 may select the input driven bymultiplexer 588 which in turn may select the input driven by register560 as directed by the logic exclusive OR gate 580. During step 855, theconfigurable register circuitry may generate a status signal and routethe status signal to an additional output, thereby providing a signalindicating that an error was detected. For example, configuration memory587 may direct multiplexer 586 to select the input driven by logicexclusive OR gate 580.

In response to detecting that the stored first signal and the storedselected signal have the same value, the configurable register circuitrymay route the stored first signal from the first register to an outputduring step 840. During step 850, the configurable register circuitrymay route the stored selected signal to an additional output.

The method and apparatus described herein may be incorporated into anysuitable electronic device or system of electronic devices. For example,the method and apparatus may be incorporated into numerous types ofdevices such as microprocessors or other ICs. Exemplary ICs includeprogrammable array logic (PAL), programmable logic arrays (PLAs), fieldprogrammable logic arrays (FPGAs), electrically programmable logicdevices (EPLDs), electrically erasable programmable logic devices(EEPLDs), logic cell arrays (LCAs), field programmable gate arrays(FPGAs), application specific standard products (ASSPs), applicationspecific integrated circuits (ASICs), just to name a few.

The integrated circuit described herein may be part of a data processingsystem that includes one or more of the following components; aprocessor; memory; I/O circuitry; and peripheral devices. The integratedcircuit can be used in a wide variety of applications, such as computernetworking, data networking, instrumentation, video processing, digitalsignal processing, or any suitable other application where the advantageof using high-speed serial interface circuitry is desirable.

Although the method operations were described in a specific order, itshould be understood that other operations may be performed in betweendescribed operations, described operations may be adjusted so that theyoccur at slightly different times or described operations may bedistributed in a system which allows the occurrence of the processingoperations at various intervals associated with the processing, as longas the processing of the overlay operations are performed in a desiredway.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention. Theforegoing embodiments may be implemented individually or in anycombination.

What is claimed is:
 1. An integrated circuit, comprising: a first memoryelement that produces a first configuration bit; a second memory elementthat produces a second configuration bit; a first multiplexer thatreceives the first configuration bit from the first memory element andfirst and second signals from first and second inputs, wherein the firstmultiplexer selects between the first and second signals based on thefirst configuration bit; a second multiplexer that receives the secondconfiguration bit, a first clock signal, and a delayed first clocksignal, wherein the second multiplexer selects between the first clocksignal and the delayed first clock signal to generate a second clocksignal based on the second configuration bit; a first register triggeredbased on the first clock signal, wherein the first register receives andstores the first signal from the first input; a second registertriggered based on the second clock signal, wherein the second registerreceives and stores a selected one of the first and second signals fromthe first multiplexer; and a comparator that receives the stored firstsignal from the first register and the stored selected one of the firstand second signals from the second register, the comparator generating astatus signal based on a comparison of the stored first signal and thestored selected one of the first and second signals.
 2. The integratedcircuit of claim 1, wherein the comparator further comprises: a logicexclusive OR gate that receives the stored first signal from the firstregister and the stored selected one of the first and second signalsfrom the second register.
 3. The integrated circuit of claim 1, furthercomprising: a third memory element that produces a third configurationbit; and a third multiplexer that receives the third configuration bitfrom the third memory element, the status signal from the comparator andthe stored selected one of the first and second signals from the secondregister, and wherein the third multiplexer selects between the statussignal and the stored selected one of the first and second signals basedon the third configuration bit.
 4. The integrated circuit of claim 1,further comprising: a third memory element that produces a thirdconfiguration bit; and a logic exclusive OR gate that receives the firstclock signal and the third configuration bit from the third memoryelement, and wherein the logic exclusive OR gate is operable to invertthe first clock signal to generate the second clock signal based on thethird configuration bit.
 5. The integrated circuit of claim 1, furthercomprising: a third multiplexer that receives the status signal from thecomparator, the stored first signal from the first register, and thestored selected one of the first and second signals from the secondregister, and wherein the third multiplexer selects between the storedfirst signal and the stored selected one of the first and second signalsbased on the status signal to produce a third multiplexer output signal.6. The integrated circuit of claim 5, further comprising: a third memoryelement that produces a third configuration bit; and a fourthmultiplexer that receives the third configuration bit from the thirdmemory element, the third multiplexer output signal from the thirdmultiplexer, and the stored first signal from the first register, andwherein the fourth multiplexer selects between the third multiplexeroutput signal and the stored first signal based on the thirdconfiguration bit.
 7. The integrated circuit of claim 1, furthercomprising: a delay element that receives the first clock signal anddelays the first clock signal by a predetermined time duration togenerate the delayed first clock signal.
 8. The integrated circuit ofclaim 1, further comprising: a third memory element that produces athird configuration bit; and a logic AND gate that receives the statussignal from the comparator and the third configuration bit from thethird memory element, wherein the logic AND gate performs a logic ANDoperation of the status signal and the third configuration bit toproduce an output signal.
 9. The integrated circuit of claim 1, whereinthe first register is implemented in a logic region of a programmablelogic device.
 10. A method for operating an integrated circuit, themethod comprising: with configuration memory, storing configurationdata; with selection circuitry, receiving first and second signals andselecting between the first and second signals based on theconfiguration data to produce a selected signal; with a first register,storing the first signal based on a first clock signal; with delaycircuitry, generating a second clock signal by delaying the first clocksignal; with additional selection circuitry, selecting between the firstclock signal and second clock signal based on the configuration data toproduce a selected clock signal; with a second register, storing theselected signal based on the selected clock signal; and with controlcircuitry, determining whether the stored first signal is different fromthe stored selected signal.
 11. The method of claim 10, wherein thefirst clock signal has a first clock rate and wherein the second clocksignal has a second clock rate that is the same as the first clock rate.12. The method of claim 10, further comprising: with configurableinterconnect circuitry, routing the stored first signal to an output.13. The method of claim 12, further comprising: in response todetermining that the stored first signal is different from the storedselected signal, routing the stored selected signal to the output. 14.The method of claim 10, further comprising: with configurableinterconnect circuitry, routing the stored selected signal to an output.15. The method of claim 14, further comprising: in response todetermining that the stored first signal is different from the storedselected signal, generating a status signal; and with configurableinterconnect circuitry, routing the status signal to the output.
 16. Themethod of claim 10, further comprising: in response to determining thatthe stored first signal is different from the stored selected signal,routing the stored selected signal to the first register.
 17. The methodof claim 10, further comprising: with a bit stream, providing theconfiguration data to the configuration memory.
 18. A method foroperating register circuitry in a programmable logic region, the methodcomprising: with a first register in the programmable logic region,receiving and storing a data signal at based on a clock signal; with adelay circuit, producing a delayed clock signal based on the clocksignal; with a multiplexer, selecting between the data signal and anadditional data signal to produce a selected data signal; with a secondregister in the programmable logic region, receiving the selected datasignal from the multiplexer and storing the selected data signal basedon a selected one of the clock signal and the delayed clock signal; witha comparator in the programmable logic region, receiving the stored datasignal from the first register at a first input and the stored selecteddata signal from the second register at a second input; with thecomparator, producing a status signal based on a comparison of thestored data signal and the stored selected data signal.
 19. The methodof claim 1, further comprising: with a second multiplexer, receiving thestored selected data signal from the second register, the status signalfrom the comparator, and a predetermined configuration bit from a memoryelement; and selecting between the stored selected data signal from thesecond register and the status signal from the comparator based on thepredetermined configuration bit.
 20. The method of claim 18, the methodfurther comprising: with the multiplexer, receiving the data signal, theadditional data signal, and a predetermined configuration bit from amemory element, wherein the multiplexer produces the selected datasignal based on the predetermined configuration bit.
 21. The method ofclaim 20, wherein an additional multiplexer is coupled to the secondregister and wherein the predetermined configuration bit is a firstpredetermined configuration bit, the method further comprising: with theadditional multiplexer, receiving the clock signal, the additionaldelayed clock signal, and a second predetermined configuration bit froma memory element; and with the additional multiplexer, selecting betweenthe clock signal and the delayed clock signal based on the secondpredetermined configuration bit.